1. Technical Field
The present invention generally relates to programmable logic arrays (PLAs), and more particularly to a dynamic PLA having a reduced propagation delay.
2. Description of the Related Art
Microprocessor control logic has a direct impact on processing frequency and therefore processing power. Logic circuits are required that can evaluate a large number of inputs and produce a large number of outputs flexibility in determining the logical output-from-input dependencies.
A programmable logic array (PLA) is an integrated circuit device that incorporates fixed sets of AND and OR logic gates or similar functions such as NAND, NOR, XOR or XNOR with one or more interconnect planes used to create several logical combinatorial outputs from several logical inputs. The interconnect planes in a mask PLA are usually metallization layers that can be redesigned and deposited during a production run without redesigning the semiconductor layers of the device. The depositing of the mask can be performed by vapor deposition of aluminum or other metals using techniques well known in the art. The mask connects devices within an interconnect array or "plane" comprising two sets of conductors: a set of logic inputs and a set of logic gate inputs. The sets of conductors are coupled together with devices that create a logic contribution from the logic inputs to the logic gate inputs. Fuse programmable logic arrays allow the programming of a device after manufacture by using a programming unit or appropriate in-circuit electronics to allow the programming of a device.
Propagation delay of a logic circuit is the time it takes for a change of state at the input to be reflected in the state at the output. In high speed logic, it is desirable to reduce propagation delay from logic inputs to the final evaluated outputs. In asynchronous logic, an output is valid only after all of the inputs that form part of the logic equation have propagated through the gates to the output. In synchronous logic, the maximum clocking rate of the device is set by the validity of the combinatorial input to the latch, which is determined by the time it takes for all of the inputs to propagate to the input of the register latching the output.
Dynamic PLA's propagate pulses instead of voltage levels. An intermediate plane is preset to logic state, then individual nodes are reset or left alone, depending the result of the logic evaluation of the input plane. The output plane combines these intermediate results to reset output plane devices, to produce a final result. Thus, the logic levels exist as pulses in between preset intervals, that are typically provided by a synchronous system clock.
As the number of terms in the intermediate plane in a dynamic PLA increases, the size of the wire used to interconnect the input plane gate outputs and the number of gates loading these wires also increases. As a result, the time required to discharge the preset voltage from the node forming the intermediate plane output also increases because of the added capacitance. So, propagation delay increases as more logical terms are implemented by the output plane of a PLA.
It would therefore be desirable to improve dynamic mask programmable logic arrays and other topologies so that propagation delay is reduced. It would further be desirable to improve dynamic mask PLAs to make them suitable for implementing the control logic in microprocessors.